FIGS. 17 and 18 are a plan view and a cross-sectional view showing the structure of a power semiconductor device 70 as an example of a conventional power semiconductor device. FIG. 18 is the cross section taken along the line X—X in FIG. 17.
In FIGS. 17 and 18, a bottom substrate 12 has a rectangular shape in plan view and is made of a material having good thermal conductivity, e.g. metal, and two insulating substrates 3 are disposed in parallel at an interval on a main surface of the bottom substrate 12 and three sets of devices, each including one IGBT (Insulated Gate Bipolar Transistor) device 1 and one diode device 2, are disposed on each insulating substrate 3.
Also on the main surface of the bottom substrate 12, a main collector electrode terminal 4 and a main emitter electrode terminal 5 are disposed in the region between the two insulating substrates 3, with a C-shaped control emitter relay terminal plate 39 surrounding the main collector electrode 4 and the main emitter electrode terminal 5. The main collector electrode terminal 4 and the main emitter electrode terminal 5 are provided on the bottom substrate 12 with a main collector substrate 41 and a main emitter substrate 51 interposed therebetween.
Further, gate relay terminal plates 36 are disposed along the insulating substrates 3 at both ends of the bottom substrate 12 in the direction along the row of the insulating substrates 3. The gate electrode of each IGBT device 1 is electrically connected to the nearby gate relay terminal plate 36 through a wire interconnection WR, and the anode of each diode device 2 is electrically connected to the nearby control emitter relay terminal 39 through a wire interconnection WR. The control emitter electrode of each IGBT device 1 is electrically connected to the anode of the diode device 2 in the same set through a wire interconnection WR.
Now, FIG. 19 shows the connection of the IGBT devices 1 and diode devices 2. As shown in FIG. 19, six IGBT devices 1 are connected in parallel and the diode devices 2 are connected with them in parallel in a one-to-one manner in such a direction that the forward current flows back to the IGBT device 1, so that they can function as free-wheel diodes. The IGBT devices 1 have their respective gate electrodes connected to a gate derive terminal 66 in common and their control emitter electrodes (equivalent to the emitter electrodes) connected to a control emitter derive terminal 69 in common and also to the main emitter electrode terminal 5.
The control emitter derive terminal 69 is used to drive the IGBT devices 1; a gate-emitter voltage (e.g. about 15 V) is applied between the control emitter derive terminal 69 and the gate derive terminal 66 to drive the IGBT devices 1.
In FIGS. 17 and 18, the two gate relay terminal plates 36 are electrically connected in common to the gate derive terminal 66 through an interconnection bar 46 extending parallel to the main surface of the bottom substrate 12, and the control emitter relay terminal plate 39 is connected to the control emitter derive terminal 69 through an interconnection bar 49 extending parallel to the main surface of the bottom substrate 12.
The gate derive terminal 66 vertically extends from the gate relay terminal plate 36 on the left side in FIG. 17 and the interconnection bar 46 is connected to the gate derive terminal 66.
The control emitter derive terminal 69 stands parallel to the gate derive terminal 66 and vertically extends above the gate relay terminal plate 36 on the left side in FIG. 17; while the gate derive terminal 66 is electrically connected to the gate relay terminal plate 36, the control emitter derive terminal 69 is not in contact with the gate relay terminal plate 36.
A rectangular box-like resin case 11 surrounds the bottom substrate 12 and a resin material is sealed in the space defined by the bottom substrate 12 and the resin case 11.
The gate derive terminal 66, the control emitter derive terminal 69, the main collector electrode terminal 4, and the main emitter electrode terminal 5 vertically extend to protrude through an opening in the resin case 11 so that they can be electrically connected to the outside.
Note that, for convenience, FIGS. 17 and 18 do not show means electrically connecting the emitter electrodes and the main emitter electrode terminal 5 and means electrically connecting the collector electrodes of the IGBT devices 1 and the main collector electrode terminal 4, since they are not closely related to this invention.
FIGS. 20 and 21 are a plan view and a cross-sectional view showing the structure of a power semiconductor device 80 as an example of a conventional power semiconductor device.
The structure of the power semiconductor device 80 is basically the same as that of the power semiconductor device 70 described referring to FIGS. 17 and 18 and the same components are shown with the same reference characters and are not described again here. FIG. 21 is the cross section taken along the line Y—Y in FIG. 20.
In FIGS. 20 and 21, a rectangular control board CB is disposed to almost entirely cover the area above the bottom substrate 12. The gate relay terminal plates 36 and the control emitter relay terminal plate 39 are electrically connected to the control board CB through gate relay terminals 88 and a control emitter relay terminal 77 that vertically extend to the control board CB.
The control board CB has control circuitry and elements for controlling operations of the IGBT devices 1 and the diode devices 2; the control circuitry is thus contained in the power semiconductor device 80 to allow it to work as an IPM (Intelligent Power Module).
The main collector electrode terminal 4 and the main emitter electrode terminal 5 are connected to a main collector derive terminal 43 and a main emitter derive terminal 53 respectively through interconnection bars 42 and 52 that extend parallel to the main surface of the bottom substrate 12.
The main collector derive terminal 43 and the main emitter derive terminal 53 vertically extend above the gate relay terminal plate 36 on the left side in FIG. 20 to protrude through the opening in the resin case 11 so that they can be electrically connected to the outside. A plurality of derive terminals OT are disposed on the top main surface of the control board CB, which protrude through the opening of the resin case 11 so that they can be electrically connected to the outside. These derive terminals OT serve as gate derive terminal and control emitter derive terminal.
FIGS. 22 and 23 are a plan view and a cross-sectional view showing the structure of a power semiconductor device 90 as an example of a conventional power semiconductor device. FIG. 23 is the cross section taken along the line C—C in FIG. 22.
In FIGS. 22 and 23, one insulating substrate 3 is disposed approximately in the center of the bottom substrate 12 that has a rectangular shape in plan view and three sets of devices, each including one IGBT device 1 and one diode device 2, are provided on the insulating substrate 3.
A control board CB is disposed adjacent to the row of the IGBT devices 1 on the insulating substrate 3 and the gate electrodes of the IGBT devices 1 are electrically connected to the control board CB through wire interconnections WR.
A control emitter relay terminal plate 39A having an L shape in plan view is disposed with its one side extending adjacent to the row of the diode devices 2 on the insulating substrate 3 and the respective anodes of the diode devices 2 are electrically connected to the control emitter relay terminal plate 39A through wire interconnections WR. The control emitter electrodes of the IGBT devices 1 are electrically connected to the anodes of the diode devices 2 in the respective sets through wire interconnections WR.
Another side of the emitter relay terminal plate 39A extends parallel to the insulating substrate 3 and the control board CB, and is electrically connected to the control board CB through a wire interconnection WR. An derive terminal OT vertically extends from the main surface of the control board CB; given control signals are externally applied to the control board CB through the derive terminal OT and given signals are externally outputted therethrough from the control board CB.
The main collector electrode terminal 4 and the main emitter electrode terminal 5 are located in the edge portion opposite to the control board CB. The main collector electrode 4 terminal and the main emitter electrode terminal 5 vertically extend to protrude through the opening of the resin case 11 so that they can be electrically connected to the outside.
As described above, in the conventional power semiconductor devices 70 to 90, the gate relay terminal plate 36 is disposed next to the IGBT devices 1 so that the wire interconnections WR electrically connecting the gate electrodes of the IGBT devices 1 and the gate relay terminal plate 36 are equal in length, and the emitter relay terminal plate 39 or 39A is disposed next to the diode devices 2 so that the wire interconnections WR electrically connecting the anodes of the diode devices 2 and the emitter relay terminal plate 39 or 39A are equal in length. This reduces differences in impedance caused by differences in length among the wire interconnections WR, thus preventing imbalance in the main current flowing to the IGBT devices 1; however, these devices have the following problems.
That is to say, the power semiconductor device 70 requires the interconnection bar 46 to electrically connect the gate relay terminal plates 36 located at both ends of the bottom substrate 12, and also requires the interconnection bar 49 to connect the emitter relay terminal plate 39 to the control emitter derive terminal 69. The provision of the interconnection bars 46 and 49 restricts the layout of the IGBT devices 1 and the diode devices 2, and also a process for providing the interconnection bars 46 and 49 is required and the number of parts is increased, leading to an increase in manufacturing cost.
In the power semiconductor device 80 working as an IPM, the control board CB entirely covers the area above the bottom substrate 12, so that the main circuit terminals, i.e. the main collector electrode terminal 4 and the main emitter electrode terminal 5, have to be connected respectively through the interconnection bars 42 and 52 extending parallel to the main surface of the bottom substrate 12, to the main collector derive terminal 43 and the main emitter derive terminal 53 located at an end of the bottom substrate 12; it is thus difficult to make electric connections to the outside, and the long main circuit interconnections increase inductance and may affect the performance of the semiconductor device by, e.g. increasing the surge voltage.
In the power semiconductor device 90, also working as an IPM, the control board CB is disposed on the bottom substrate 12, so that the main collector electrode terminal 4 and the main emitter electrode terminal 5 can be easily connected electrically to the outside; however, the provision of the control board CB limits the area for installation of the IGBT devices 1 and the diode devices 2, which limits the number and layout of the power semiconductor elements installed.